An assortment of clock-generation circuits including clock drivers, clock multipliers, and clock synthesizers are commonly used in state-of-the-art digital systems for various applications. These applications include component-to-component and board-to-board skew compensation, high-speed serializer-deserializer systems, and on-chip/off-chip synchronizers.
These clock-generation circuits are typically built using either phase-locked loop (PLL) or delay-locked loop (DLL) techniques. More information on PLL and DLL techniques can be found Horowitz, M. A., Sidiropoulos, S., “A semidigital dual delay-locked loop,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 11, NOVEMBER 1997, pp 1683–1692 (herein “Horowitz '97”), incorporated herein by reference in its entirety.
Some of the issues associated with these clock-generation techniques include the rate of locking of the circuit, the determination of the locked state, and detection and correction of the incidence of false lock.
Generally, lock detection for clock-generation circuits involves comparing two counters over an interval, one driven by the reference input and the other driven by the clock generator circuit output. A matched count between the two counters at the end of the interval is typically considered a locked state. In clock-multiplication circuits, a divider is commonly placed between the clock multiplier circuit output and the output counter. In this way, a match between the input clock counter and the output counter over an interval confirms that the clock-generation circuit is multiplying the clock by the appropriate value and maintaining lock to the resolution of the interval.
In some multiphase clock-generation circuits based on DLL techniques, a multiple-output-tap, digital delay line is fed with a reference clock and the delay of the line is controlled by the voltage output of a charge pump. The charge pump is, in turn, charged or discharged by a phase detector. The phase detector compares the reference clock with the delayed version of the reference clock produced of the delay line. When the circuit is functioning properly, the phase detector charges or discharges the charge pump to adjust the delay line control-voltage so that the delay from input to output of the delay line is one period of the reference clock. In this way, each of the other taps of the delay line will correspond to a copy of the reference clock delayed by a fraction of the clock period. For example, if the clock period is T and there are N taps in the delay line, the nominal delay between taps will be T/N. As long as the overall delay is T +/− some limited error, the DLL is considered to be locked. In some circumstances, these circuits can fail to lock or may falsely lock to an improper phase or edge of a harmonic of the reference clock (e.g., harmonic lock). In this case, an approach is needed to detect and potentially correct this situation. One such approach is discussed in Foley, D. J., Flynn, M. P., “CMOS DLL Based 2V, 3.2 ps Jitter, 1 GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator,” Proc. IEEE Custom Integrated Circuits Conf., May 2000, pp. 371–374 (herein “Foley '00”), incorporated herein by reference in its entirety.